The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus, the buffer chip forming an interface to an external memory main bus.
So-called buffer chips will become necessary in future for very fast and high-density memory architectures such as, for example, DDR-III DRAMs. FIG. 1 illustrates a memory system of this type, in which the buffer chips 110, 210 which are situated on respective memory modules 100, 200 are connected in concatenated fashion to a memory main bus 400, which leads to a memory controller 300. On the buffer chips 110, 210, a switching arrangement S ensures that data are read from, or written to, the respectively addressed memory module 100 or 200 only. The Roman numerals I, II, III and IV are used to designate individual memory groups each having a plurality of memory chips which are located one behind the other in a row on the memory modules 100 and 200. The buffer chips 110, 210 convert the so-called “stub bus”, as is used nowadays in DDR and DDR-II systems, into a type of hierarchical bus system in which only point-to-point or point-to-two-point connections now occur. Connections of this type allow data transfer rates of well above one Gbps. In addition, cascading allows the concatenation of a large number of buffer chips and the realization of memory systems having a very large number of memory chips on just one memory main bus 400.
FIG. 2 illustrates in the form of a diagrammatic layout view, the manner in which a memory module (DIMM) having a buffer chip 110 (HUB) and eight memory chips can be internally constructed. Clock signal lines, which are depicted by dash-dotted lines, and command and address bus lines (C/A), which are depicted by dashed lines, are driven centrally by the buffer chip 110, successively routed to the memory chips 101, 102, . . . 108 (DRAMs) in a so-called fly-by topology and terminated at the end by means of terminations a1, a2, b1, b2 in order to avoid signal reflections. The data bus lines (DQ) (illustrated by means of solid lines in FIG. 2) of the DRAMs are connected to the buffer chip 110 separately in the form of point-to-point connections.
The propagation time of the signals on the abovementioned connecting lines will play a significant part at the high frequencies at which future computer systems, and thus the memory systems thereof, will be operated. 200 ps for each path (buffer chip to DRAM and DRAM to DRAM) shall respectively be assumed below for said propagation time. All signals (CLK, C/A, DQ, DQS) therefore require 200 ps in order to pass from the buffer chip 110 to the first DRAM (for example 104) and 800 ps in order to pass from the buffer chip 110 to the fourth DRAM (for example 101). Since the clock signal CLK and the command and address signal C/A have the same propagation time, commands and addresses can be transmitted without any problems from the buffer chip 110 to the respective DRAM chip. The same applies to the transmission of write data (DQ, DQS) to the DRAMs. From the point of view of the overall system, the fact that the actual write operation in the DRAMs respectively takes place at a different time is only of secondary importance.
If data are to be read from the DRAMs, the following problem arises: the DRAM chips receive the read command at different times on account of the propagation times of the CLK signals and the C/A signals on the bus. The difference between the first and the last DRAM is 600 ps in our example. After a certain amount of time, which shall be assumed to be the same for all DRAMs, the DRAM chips begin to send their data back to the buffer chip 110. The propagation time from the DRAM chip to the buffer chip now again depends on the position of the DRAM chip on the memory module (DIMM), the propagation time in the case of this arrangement being longest for that DRAM chip which received the command last. The data will therefore arrive at the buffer chip 110 in a temporally offset manner, to be precise in a manner respectively offset by twice the propagation time from the buffer chip 110 to the DRAM chip. 1200 ps=1.2 ns therefore elapse from the first data items to the last data items.
This time offset in the read data either limits the maximum operating frequency to values which are decidedly less than 800 MHz (=1.125 ns) or must be compensated for by means of a complicated circuit in the buffer chip, which will lead to the data being delayed further since the earliest data can be forwarded in a manner delayed by at least 1.2 ns plus the processing time of the compensating circuit.